To tackle the increasing complexity of digital electronic circuits, designers need faster and more accurate methods for statically analyzing the timing of such circuits, particularly in light of ever-shrinking product development times.
The complexity of designing such circuits is often handled by expressing the design in a high-level hardware description language (HLHDL).
HLHDLs allow the designer to save design time by permitting him or her to express the desired functionality at the register transfer level (RTL) of abstraction or higher. The high-level HDL description is then converted into an actual circuit through a process, well known to those of ordinary skill in the art as "synthesis," involving translation and optimization.
HLHDLs describe, directly or indirectly, the two main kinds of circuit entities of an RTL circuit description: i) state devices or sequential logic which store data upon application of a clock signal, and ii) combinational logic. The state devices typically act as either: i) an interface between conceptually distinct circuit systems, or ii) storage for the results of functional evaluation performed by the combinational logic.
In the process of digital circuit design, static timing analysis is often useful in order to verify that the design produced, in addition to being functionally correct, will perform correctly at the target clock speeds. For similar reasons, it would be useful to apply, as efficiently as possible, static timing analysis to the synthesis process.